Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!ucbvax!SIUCVMB.CDALE.SIU.EDU!ST6267 From: ST6267@SIUCVMB.CDALE.SIU.EDU ("Jerome Grimmer") Newsgroups: sci.electronics Subject: Re: ECL logic computers ? Message-ID: <9106271942.AA06031@ucbvax.Berkeley.EDU> Date: 27 Jun 91 20:40:16 GMT Sender: daemon@ucbvax.BERKELEY.EDU Lines: 38 John West writes: >rbennet1@gara.une.oz.au (Robert Bennetts) writes: >> can anybody out there tell me why ECL logic is not used to construct >>computers (to my knowledge anyway) considering the quite fast speeds it can >>run at.I know it uses more power than CMOS logic, >>...but if it could >>run at the above speed [400-500MHz], wouldn't it be worth the effort. > >As far as I'm aware, the main reason is price. ECL is not cheap. Some >high-end machines do in fact use it, and they benefit from the extra >speed. But you pay for it. ECL chips are low-density (transistor size, >power consumption (too many gates and it melts)). Also, to run at >500MHz, you'd need rather fast RAM. OK, you say - build that with ECL as >well. Unfortunately... a few meg of ECL SRAM would fill a VERY large >box, require some very expensive cooling, and cost an absolute FORTUNE!. >People like their PCs small, cheap to buy and cheap to run. You could >run an ECL CPU with normal DRAM, but you'd lose almost all of the extra >speed. While this is true that ECL SRAM would fill a large box and be very expensive, disregarding price, an ECL computer is still possible and you could use normal DRAM without losing most of the extra speed, your processor would necessarily be larger physically. You would need to endow it with LOTS of registers (ala RISC I) and probably it would be desirable to force arithmetic instructions to work with registers only. An internal stack for storing return addresses would also be an advantage. If I were to design this, I would also set up some ECL SRAM for a cache memory, (oh, say 64K or so, depending upon the total addressable space of the computer) to further increase speed while still being able to use normal DRAMS for main memory. I think that in time (perhaps shorter than we think) CMOS may pass up current ECL specifications for speed. Jerome Grimmer 1st yr Senior EE at Southern Illinois University-Carbondale. ST6267@siucvmb.cdale.siu.edu (Hey, it's a 5-yr program! :-)) ST6267@SIUCVMB.BITNET ap429@cleveland.freenet.edu <--where I read my news.