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From: rpw3@rigden.wpd.sgi.com (Rob Warnock)
Newsgroups: sci.electronics
Subject: Re: ECL logic computers ?
Message-ID: <113793@sgi.sgi.com>
Date: 28 Jun 91 03:14:15 GMT
References: <7183@gara.une.oz.au> <1991Jun27.052307.26836@uniwa.uwa.oz> <31917@hydra.gatech.EDU>
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Reply-To: rpw3@sgi.com (Rob Warnock)
Organization: Silicon Graphics, Inc., Mountain View, CA
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In article <31917@hydra.gatech.EDU> gt0869a@prism.gatech.EDU
(WATERS,CLYDE GORDON) writes:
+---------------
| Another reason is that ECL seems to be a little (lot?) more noise-prone 
| than standard TTL logic.
+---------------

Actually, there are reasons why ECL is *less* noise-prone, as well. Since
the power supply current is almost constant (current is switched between the
two output transistors but the total amount remains approximately constant,
excluding the load) and the voltage swing is *much* less, the power spikes and
"ground bounce" of TTL and high-speed CMOS are almost completely eliminated.

+---------------
| Flipped bits and other errors caused by voltage transients on the data
| lines can cause problems.
+---------------

But ECL runs with lower-impedance wiring, typically 50 ohms instead of 100+,
which makes it *less* succeptible to coupled transients. And ECL tends to
have edge rates that are closer to (or even, in some cases, *less* than)
the switching speeds, so that transition tend to be more like "ramps" than
"edges", which lessens noise.

I'm not saying ECL design is simple: you have to terminate any wire more
than a couple inches long; you have to fabricate your P.C. boards to achieve
a controlled impedance all along each wire (FORGET wire-wrap!); long wires
must use twisted pairs and differential receivers, or coax; controlling clock
skew across the board is a major nightmare. But many of these are true of
*any* high-performance logic, at today's speeds.

It still has its place...


-Rob

-----
Rob Warnock, MS-1L/515		rpw3@sgi.com		rpw3@pei.com
Silicon Graphics, Inc.		(415)335-1673		Protocol Engines, Inc.
2011 N. Shoreline Blvd.
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