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From: bcase@uiuccsb.UUCP
Newsgroups: net.arch
Subject: Re: BBN C machine? - (nf)
Message-ID: <2563@uiucdcs.UUCP>
Date: Sat, 13-Aug-83 23:28:56 EDT
Article-I.D.: uiucdcs.2563
Posted: Sat Aug 13 23:28:56 1983
Date-Received: Sun, 14-Aug-83 20:53:20 EDT
Lines: 19

#R:ucbesvax:12800006:uiuccsb:5600002:000:885
uiuccsb!bcase    Aug 13 21:32:00 1983

To expand a bit:  One of the best features of the BBN C machine is that
it has 1024 registers.  Upon procedure call, a new bank of 8 are allocated
for the new procedure context (and of course they are deallocated upon
procedure return (er, make that function call and function return)).
This mechanism reduces greatly the overhead of calling functions.  The
problem is that the contexts are isolated from their neighbors.  By over-
lapping the contexts, procedures may pass parameters back and forth.
This overlapping idea is the big win of the Berkeley RISC chip.

As far as the BBN C machine instruction set goes, it is really nothing
great.  With respect to the C programming language, some of the more
commonly occuring special cases are supported, but I wouldn't really
want to write a compiler for it.

    Brian Case
    University of Illinois (er, not any more:  I graduated.)