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Path: utzoo!linus!decvax!harpo!floyd!cmcl2!gottlieb
From: gottlieb@cmcl2.UUCP (Allan Gottlieb)
Newsgroups: net.micro.68k
Subject: bus req order in movl
Message-ID: <34501@cmcl2.UUCP>
Date: Tue, 8-Nov-83 14:46:30 EST
Article-I.D.: cmcl2.34501
Posted: Tue Nov  8 14:46:30 1983
Date-Received: Wed, 9-Nov-83 23:24:01 EST
Organization: New York University
Lines: 11

Consider a register to memory movl.  Obviously two bus
cycles are required to send the data out of the processor.
Is there some written guarentee as to which word is stored
first?  Analogous questions arise for a memory to register
movl and for memory to memory versions.

Thanks in advance
Allan Gottlieb
NY Univ.
ARPA: GOTTLIEB@NYU
uucp: {floyd,research,harpo}!cmcl2!gottlieb