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From: fostel@ncsu.UUCP
Newsgroups: net.arch
Subject: Risc Over-blown
Message-ID: <2417@ncsu.UUCP>
Date: Mon, 28-Nov-83 19:26:46 EST
Article-I.D.: ncsu.2417
Posted: Mon Nov 28 19:26:46 1983
Date-Received: Wed, 30-Nov-83 03:15:46 EST
Lines: 19



    I agree that there have been too many RISC papers, saying too little.
    Clearly, they have a good idea.  Clearly it will eventually prove its
    worth.  Perhaps other designs will try to use this neat idea.  I think
    the important step is not going to be cpus with reduced counts of
    instruction types, but rather, with reduced effort to produce a "nice"
    instruction set.  In another decade or so human written asm code will
    finally, really be gone.  Too much emphasis is still placed on the needs
    of the human coder.  Compilers are quite content to produce boring, ugly
    code that happens to be fast on a particular CPU.

    One question I have about the RICS, is whether all the space taken by the
    registers might not have been more profitably used as a high speed cache.
    Again, with a very highly restricted instruction set.  As a cache, some
    portion might be used to hold "stack-like" data as in the RISC, but some
    might also be used for the 15 instructions of a tight loop.  My intuition
    is that a cache would be more effective.
    ----GaryFostel----