Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!henry
From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: Risc Over-blown
Message-ID: <3397@utzoo.UUCP>
Date: Sat, 3-Dec-83 23:54:12 EST
Article-I.D.: utzoo.3397
Posted: Sat Dec  3 23:54:12 1983
Date-Received: Sat, 3-Dec-83 23:54:12 EST
References: <2417@ncsu.UUCP>
Organization: U of Toronto Zoology
Lines: 21

Gary Fostel asks whether it would be good to use some of the RISC's
on-chip register RAM for an instruction cache instead.  As far as I
know, the Berkeley folks have always assumed that a production RISC
would have not only the register stack but *also* an instruction cache.
In fact I've seen at least one recent paper from them on the design
of a separate cache chip, also incorporating expansion of a "tighter"
instruction format into the RISC's rather bulky instructions.  Looks
good to me.

He also suggests that the important point of the RISC is not simplicity
but the firm intent that all code be compiler-generated.  True in some
ways, but if you abandon the simplicity constraint you get a rather
more complex machine, much more like the Stanford MIPS project.  One of
the major points of the RISC concept is that a simpler design lets you
invest more resources in making the hardware fast (since the "basic"
resource requirements are much lower).  "Resources" here means things
like chip area, which are not subject to massive expansion by simply
waving a magic wand, so the simplicity really is a major win.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry