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Path: utzoo!linus!decvax!ittvax!dcdwest!sdcsvax!sdccsu3!muller
From: muller@sdccsu3.UUCP
Newsgroups: net.arch
Subject: Re: risc registers versus cache memory
Message-ID: <1355@sdccsu3.UUCP>
Date: Thu, 1-Dec-83 13:36:25 EST
Article-I.D.: sdccsu3.1355
Posted: Thu Dec  1 13:36:25 1983
Date-Received: Sun, 4-Dec-83 07:59:49 EST
References: <2417@ncsu.UUCP>
Organization: U.C. San Diego, Computer Center
Lines: 10

You can view both risc registers and cache memory as a way of reducing
memory access bottlenecks. Cache memory increases speed by reducing the
number of accesses to slower main memory. However a properly designed
risc machine and compiler can have the same effect. The large number
of registers can be used in the same manner as a cache memory. If the
compiler can generate code such that a large percentage of the operands
are in registers the number of main memory accesses are reduced.

Keith Muller
UCSD CS Dept