Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site fortune.UUCP
Path: utzoo!linus!decvax!harpo!eagle!hou5h!hou5a!hou5d!hogpc!drux3!ihnp4!fortune!lee
From: lee@fortune.UUCP
Newsgroups: net.arch
Subject: Re: Re: risc registers vs. cache memory
Message-ID: <1900@fortune.UUCP>
Date: Tue, 6-Dec-83 15:00:53 EST
Article-I.D.: fortune.1900
Posted: Tue Dec  6 15:00:53 1983
Date-Received: Fri, 9-Dec-83 02:43:01 EST
Organization: Fortune Systems, Redwood City, CA
Lines: 10

No, I disagree that cache memory and registers are the same.
Cache memory is transparent to the machine architecture,
and there is no limit (except the price ) to the amount 
of cache memory in a machine.  In order to address large
number of registers, the register identifications have to
be encoded in the instructions.  There are definitely 
limits (longer instructions) in the number of registers.

	Ed Lee
	fortune!lee