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Path: utzoo!linus!security!genrad!decvax!tektronix!paulh
From: paulh@tektronix.UUCP (Paul Hoefling)
Newsgroups: net.arch
Subject: Re: risc registers and cache
Message-ID: <1641@tektronix.UUCP>
Date: Tue, 13-Dec-83 02:17:05 EST
Article-I.D.: tektroni.1641
Posted: Tue Dec 13 02:17:05 1983
Date-Received: Fri, 9-Dec-83 04:01:51 EST
Organization: Tektronix, Beaverton OR
Lines: 23

>>  Newsgroups: net.arch
>>  Subject: Re: risc registers versus cache memory
>>  
>>  You can view both risc registers and cache memory as a way of reducing
>>  memory access bottlenecks. Cache memory increases speed by reducing the
>>  number of accesses to slower main memory. However a properly designed
>>  risc machine and compiler can have the same effect. >>>  The large number
>>  of registers can be used in the same manner as a cache memory. If the
>>  compiler can generate code such that a large percentage of the operands
>>  are in registers the number of main memory accesses are reduced. <<<
>>  
>>  Keith Muller
>>  UCSD CS Dept
>>  

How about that ?  Seymour Cray was right !!!  :-)

Happy computing...

Paul Hoefling
(...!teklabs!tektronix!paulh - usenet)
(paulh at tektronix - csnet)
(AB00PLH on Cyber)