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Path: utzoo!linus!security!genrad!decvax!harpo!floyd!vax135!ariel!jlw
From: jlw@ariel.UUCP (J.WOOD)
Newsgroups: net.arch
Subject: Re: risc registers vs. cache memory
Message-ID: <526@ariel.UUCP>
Date: Wed, 7-Dec-83 08:26:19 EST
Article-I.D.: ariel.526
Posted: Wed Dec  7 08:26:19 1983
Date-Received: Fri, 9-Dec-83 05:54:20 EST
References: <1900@fortune.UUCP>
Organization: AT&T-ISL, Holmdel, NJ
Lines: 28

There have been two microprocessors that I know about
that have put the registers in regular memory; the
BTL BELMAC-8 and the TI 9900.  In addition I believe
that the registers of some of the UNIVAC 1100 series
machines either were or appeared to be in regular
address space, but I could be wrong on this.  I
disagree that registers and cache must be architecturally
different.  Putting the registers in address space
and then providing a cache with an access time
the same as on-board registers seems to me to
be a big win.  The cache management algorithms
available now would be ideal for the management
of a register file that is as big as all outdoors.
A possible improvement in performance in the case
of a register file miss could be obtained by
marking tha page as registers and if the register
file pointer is being pushed and causes a miss
then cache memory is only allocated, and the
read through is omitted.



					Joseph L. Wood, III
					AT&T Information Systems
					Laboratories, Holmdel
					(201) 834-3759
					ariel!jlw