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Path: utzoo!linus!decvax!tektronix!orca!andrew
From: andrew@orca.UUCP (Andrew Klossner)
Newsgroups: net.arch
Subject: Re: risc registers vs. cache memory
Message-ID: <374@orca.UUCP>
Date: Thu, 8-Dec-83 11:00:56 EST
Article-I.D.: orca.374
Posted: Thu Dec  8 11:00:56 1983
Date-Received: Sun, 11-Dec-83 00:49:08 EST
References: <1900@fortune.UUCP> <526@ariel.UUCP>
Organization: Tektronix, Wilsonville OR.
Lines: 25

A historical note on putting registers in the address space:

The PDP-10 architecture, based on 36-bit words, includes sixteen
registers which occupy locations 0 through 17 (octal) in the address
space.  In many ways this bit of orthogonality made programming and
code generation easier.  In other ways, it was an open invitation to
the following "clever" coding technique: moving small compute-intensive
loops into the registers.

As example, the TECO editor, when inserting a character into its memory
buffer, had to visit successive words, shift each right 7 bits, insert
a 7-bit byte from the previous word, etc.  It did this with about 12
instructions, using 4 registers (numbers approximate from moldy
brainware memory).

The technique of putting loops in the registers proved to be successful
and was adopted by a variety of assembly language programs.  When the
current CPU, the KL10, came out, it turned out that, with its lightning
fast memory cache, fetching instructions from memory was *faster* than
fetching them from the registers, and all these programs had
intricately developed, carefully optimized register loops which ran
slower than they would had they been left in memory.

  -- Andrew Klossner   (decvax!tektronix!tekecs!andrew)      [UUCP]
                       (tekecs!andrew.tektronix@rand-relay)  [ARPA]