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From: lee@fortune.UUCP (Ed Lee)
Newsgroups: net.arch
Subject: (Re: x 3) risc registers and cache
Message-ID: <1939@fortune.UUCP>
Date: Fri, 9-Dec-83 17:32:24 EST
Article-I.D.: fortune.1939
Posted: Fri Dec  9 17:32:24 1983
Date-Received: Sun, 11-Dec-83 02:30:13 EST
Organization: Fortune Systems, Redwood City, CA
Lines: 16

If a machine can access external storages ( memory )
as fast ( or slow ) as internal storages ( registers or cache ),
then there are no needs for registers at all.  But for many
machines, internal storages are much faster than external storages.
If I understand it correctly, risc registers make uses of the
speed difference to improve risc machine performance.  Risc registers
are faster because they are directly addressable by instructions.
I am not saying that risc registers and cache cannot produce the
same result, but the techniques are different.  The argument for
risc machine is that these differences may be visible to hardware
designers or machine language programmers, but there are invisible
to the high-level programmers.

	Ed Lee
	{amd70, ihnp4, harpo}!fortune!lee