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Path: utzoo!linus!security!genrad!decvax!cca!ima!haddock!stevel
From: stevel@haddock.UUCP
Newsgroups: net.arch
Subject: Re: Risc Over-blown - (nf)
Message-ID: <7@haddock.UUCP>
Date: Sat, 10-Dec-83 23:35:21 EST
Article-I.D.: haddock.7
Posted: Sat Dec 10 23:35:21 1983
Date-Received: Tue, 13-Dec-83 01:49:29 EST
Lines: 20

#R:ncsu:-241700:haddock:9500002:000:838
haddock!stevel    Nov 30 15:04:00 1983

One of the features of RISC that I have not seen mentioned
is that it is much easier to write CORRECT compilers for them.

There are not so many instruction interations to screw up on in a
RISC chip. If you do good flow analysis at the intermediate code
stage it should then be relativly easy to write code generators
for different RISC implimentations.

This allows CPU designers to change technologies (NMOS to ECL to
GaAs) and take advantage of gate implimentation considerations to
modify the instruction set.  The new code generator would be
fairly easy to create and then the whole system would come up and
run.  It would only take about 1 to 1.5 man years to get the
system software ported (i.e. UNIX) instead of having to spend the
current 3-5 man years.

Steve Ludlum, decvax!yale-co!ima!stevel, {ucbvax|ihnp4}!cbosgd!ima!stevel