Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!linus!decvax!harpo!floyd!vax135!ariel!hou5f!hou5e!hou5d!hogpc!drux3!ihnp4!inuxc!pur-ee!uiucdcs!parsec!ctvax!uokvax!andree From: andree@uokvax.UUCP Newsgroups: net.arch Subject: Re: Re: risc registers vs. cache memory - (nf) Message-ID: <4425@uiucdcs.UUCP> Date: Sat, 10-Dec-83 20:48:34 EST Article-I.D.: uiucdcs.4425 Posted: Sat Dec 10 20:48:34 1983 Date-Received: Tue, 13-Dec-83 03:10:24 EST Lines: 19 #R:ariel:-52600:uokvax:9900001:000:692 uokvax!andree Dec 9 08:13:00 1983 Johnson (at BTL) came up with a similar scheme. One of his 32 bit designs had no registers, just lots of cache. The CPU kept pointers to memory that marked the top/bottom of the cache address. The idea was to keep the top of stack in cache, so stack-oriented languages would win big. He did studies of most of the Unix tools, and found that 80%+ (I think that is the correct figure) ran in less than 512 bytes of stack, and only one program (this number I know to be correct) took more than 1024 bytes of stack - Ritches recursive descent C compiler. This seems like a major win to me. I'd be interested in hearing from anybody who is working on such a machine, or anything similar.