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From: b-davis@utah-cs.UUCP (Brad Davis)
Newsgroups: net.arch
Subject: Re: risc registers vs. cache memory
Message-ID: <2301@utah-cs.UUCP>
Date: Sat, 10-Dec-83 11:56:03 EST
Article-I.D.: utah-cs.2301
Posted: Sat Dec 10 11:56:03 1983
Date-Received: Tue, 13-Dec-83 05:39:14 EST
References: <1900@fortune.UUCP>, <526@ariel.UUCP> mh3bc1.108
Lines: 18

Since the DEC-10's and 20's have their 16 registers mapped to the
first 16 words of memory a small loop could be inserted into them
and would execute very fast (no memory references).  The problem 
with this is that it TOPS-20 you could deposit data into memory and 
start execution from the EXEC command processor.  If you put a jump 
to self in a register and started it executing then you can load the
machine badly since there is no swapping, memory access, and the 
program is all ready to run.  With only 1% of the machine guarrenteed
I have been able to get over 30% on an overloaded machine.  If the 
machine is not loaded then the figure has gone up to 90+%.  This is 
not to suggest that anyone try this.  I was doing this as an experiment
only.  I think that it is a failure of the system that allows this to 
happen.


					Brad Davis
					..!harpo!utah-cs!b-davis
					b-davis@utah-cs.ARPA