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From: howard@metheus.UUCP (Howard A. Landman)
Newsgroups: net.arch
Subject: Re: Q's about RISC and HLLs - (nf)
Message-ID: <191@metheus.UUCP>
Date: Thu, 15-Dec-83 17:37:42 EST
Article-I.D.: metheus.191
Posted: Thu Dec 15 17:37:42 1983
Date-Received: Sat, 17-Dec-83 07:43:44 EST
References: <580@inmet.UUCP>
Organization: Metheus, Portland Oregon
Lines: 46


In partial answer to Steve Stein (decvax!harpo!inmet.szs):

	FIRST QUESTION: Is it the "memory management" access descriptor BS
	that slows it down or the complexity of the 432's ISA in general???

I'm sure Intel has thought about this a lot.  But have you looked at the
article on the 432 by people at Berkeley (including some RISC-ers)?  The
full reference was published on the net a month or so ago.  Look for an
article by wateng!pparkinson.

	The dearth of real performance info for RISC is frustrating.
	Details in Radin's and Patterson's stuff are too sketchy.

Why don't you ask some the people involved?  I'm sure that Dave Patterson
and Manolis Ketevenis, for example, would have data or references (or both)
that you would find useful.  Try ucbvax!pattrsn and ucbvax!kateveni; these
used to be valid.  And the commercial RISC-oids should be more than happy
to deluge you with performance info (anyone at Pyramid Technology listening?).

	Does anyone have some size/time comparisons along with the
	RISC "assembly" code for some common algorithms??

The size comparisons were published long ago for RISC I.  Again, have you read
all the references in wateng!pparkinson's listing?  The early time comparisons
were of course estimated because the chip hadn't been built yet.  More recent
papers have more accurate info based on running the actual chip.  The assembly
code for many small programs (including all the cited benchmarks) either exists
at Berkeley or can be easily recreated since it was produced by a compiler,
although there were some small diagnostic programs that were hand-coded in
assembler.

	(Side comment: It seems that at least some of the remaining
	94% of the computer design job has been thrown in the compiler
	writer's lap for RISC.)

Au contraire: writing compilers for machines with simple architectures is
EASIER than writing similar compilers for machines with complex architectures,
IF the architectures both provide adequate support for the HLL in question.
A C compiler for the RISC I was running months before the chip was finished,
and helped find several early bugs in the design.  (Recall that the chip was
designed in 5 months.)  The only sense in which your comment is true is that
library routines for floating point had to be coded.

	Howard A. Landman (one of the designers of the RISC I chip)
	ogcvax!metheus!howard