Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site lanl-a.UUCP
Path: utzoo!linus!philabs!cmcl2!lanl-a!jlg
From: jlg@lanl-a.UUCP
Newsgroups: net.arch
Subject: Re: Risc Over-blown - (nf)
Message-ID: <41@lanl-a.UUCP>
Date: Mon, 19-Dec-83 22:36:36 EST
Article-I.D.: lanl-a.41
Posted: Mon Dec 19 22:36:36 1983
Date-Received: Wed, 21-Dec-83 02:29:16 EST
References: <1124@ucbcad.UUCP>
Organization: Los Alamos National Laboratory
Lines: 25

Someone has probably mentioned this before, but the really FAST mainframe
computers on the market today are all closer to RISC than to HP superchips
or any DEC product.  This is for the reasons described in the preceeding
notes.  To operate at really high speeds, a computer has to make use of
very high power, very simple chips.  VLSI isn't fast enough -- discrete 
components are used.  To build an 80MHz machine with an unRISCy instruction
set would require a room full of components, and a nuclear power plant to 
power it.  

And if you think that mainframes are on their way out -- the parallel
machines that replace them will be too hard to program and verify if
they aren't kept simple.

Of course, my main objection to unRISCy archetectures is that they glorify
to memory buss; you just can't do anything without going to slow memory.
With enough registers (and a pipelined archetecture so memory can be referenced
asynchronously) you can perform incredible ammounts of code without being
held up for memory once.  This problem would go away if memory were as fast
as registers, but memory is always made with older technology (for price)
while registers are always state-of-the-art (for speed).

		J.L. Giles 
		Los Alamos National Lab