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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.arch
Subject: Re: (Re: x 3) risc registers and cache
Message-ID: <153@intelca.UUCP>
Date: Mon, 12-Dec-83 21:31:59 EST
Article-I.D.: intelca.153
Posted: Mon Dec 12 21:31:59 1983
Date-Received: Fri, 23-Dec-83 01:35:08 EST
References: <1939@fortune.UUCP>
Organization: Intel, Santa Clara, Ca.
Lines: 7

actually, I would think that you would still want a "register" type 
opcode, even if external memory was a fast as internal memory
since register specification takes fewer opcode bits than direct
(or pc relative?) specification...or what?
-- 
Ken Shoemaker, Intel, Santa Clara, Ca.
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