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Path: utzoo!henry
From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: (Re: x 3) risc registers and cache
Message-ID: <3430@utzoo.UUCP>
Date: Wed, 28-Dec-83 21:02:14 EST
Article-I.D.: utzoo.3430
Posted: Wed Dec 28 21:02:14 1983
Date-Received: Wed, 28-Dec-83 21:02:14 EST
References: <1939@fortune.UUCP> <153@intelca.UUCP>, <152@hou3c.UUCP>
Organization: U of Toronto Zoology
Lines: 8

It's been a long time since I read the VAX specs, and I'm too lazy to
go digging through them right now, but I believe that referencing into
the stack on the VAX takes at least 16 bits:  4 bits addressing mode,
4 bits register number, 8 bits for the smallest available offset.  This
is substantial compared to 5 bits for a register number on the RISC.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry