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From: eich@uiuccsb.UUCP
Newsgroups: net.micro
Subject: Re: Building a 68000 system - (nf)
Message-ID: <4648@uiucdcs.UUCP>
Date: Tue, 20-Dec-83 04:28:49 EST
Article-I.D.: uiucdcs.4648
Posted: Tue Dec 20 04:28:49 1983
Date-Received: Wed, 21-Dec-83 05:30:00 EST
Lines: 12

#R:sri-arpa:-1449000:uiuccsb:4400034:000:277
uiuccsb!eich    Dec 20 03:12:00 1983


sMEMR is the S-100 status line which indicates the initiation of a
memory read cycle.  It is not a dynamic RAM refresh signal; of course,
the memory board could (and the ones I've seen do) generate their own
refresh.

	Brendan Eich
	uiucdcs!uiuccsb!eich
	eich.uiuc@rand-relay