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Path: utzoo!linus!philabs!cmcl2!floyd!clyde!ihnp4!fortune!lee
From: lee@fortune.UUCP (Ed Lee)
Newsgroups: net.micro
Subject: Re: Re: building a 68000 system
Message-ID: <2080@fortune.UUCP>
Date: Wed, 21-Dec-83 17:36:11 EST
Article-I.D.: fortune.2080
Posted: Wed Dec 21 17:36:11 1983
Date-Received: Fri, 23-Dec-83 00:48:30 EST
Organization: Fortune Systems, Redwood City, CA
Lines: 18

This should belong to net.micro.s100 (if people are interested ).

	On going through the schematics, I find an output labelled sMEMR,
	on pin 47 on the s-100 bus. I believe this is the memory refresh
	line you want.

sMEMR stands for  s-100 bus MEMory Read.  I think that the confusions
came from the pre-IEEE 696 s-100 bus pin 99 (refresh).  Early s-100
computers use pin 99 to indicate that the bus masters (main CPU or DMA
devices) are not using the memory.  Memory boards should gate this
signal with internal logics to refresh dynamic memory.  However, the
refresh pin is not defined in the IEEE 696 standard.  Newer memory 
boards either look at other signals or insert wait states at appropriate
time.  I haven't been reading the spec for a while, so please check
this with your local s-100 wizard.
 
  c  / 			Ed Lee
 C. /_.  	{amd70, ihnp4, harpo}!fortune!lee