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From: mike@smu.UUCP
Newsgroups: net.micro
Subject: Re: Tandy 2000 - (nf)
Message-ID: <5176@uiucdcs.UUCP>
Date: Thu, 26-Jan-84 22:59:45 EST
Article-I.D.: uiucdcs.5176
Posted: Thu Jan 26 22:59:45 1984
Date-Received: Sat, 28-Jan-84 02:26:25 EST
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#R:bmcg:-74000:smu:14300009:000:1539
smu!mike    Jan 26 14:22:00 1984

~s80186 in Tandy 2000

	Regarding the processor compatibilty twixt the PC and the 2K:

		Although the iAPX 186 is supposed to be upward compatible from
	the iAPX 88, there are a couple of minor differences which could
	be important.  The iAPX 186 has a sixteen bit external data bus
	and is thus capable of performing true sixteen bit I/O operations.
	Peripherals which contain eight bit devices with multiple
	registers (like a UART with command and data ports) might be
	mapped to consecutive addresses for the eight bit iAPX 88 bus;
	this presents a problem for the iAPX 186, which will expect eight
	bit data from even addresses on one half of the bus and data from
	odd addresses on the other half.  I am not sure how common this
	problem might be.

		The other consideration is that the iAPX 186 has an illegal
	instruction trap.  Of course, this should not be a problem for
	working software, but one never knows.

		The 8087 NPX poses the big problem.  This chip was designed to
	reside on the local bus with an iAPX 86 or 88 and closely monitor 
	the operation of the processor's internal que.  This meant that
	both chips ran off of the same clock, a 33% duty cycle signal from
	the 8284 clock chip.  The iAPX 186 has an internal mutant of the
	8284 which produces a 50% duty cycle signal.  What's more, the
	iAPX 186's internal chip select logic becomes useless, since the
	8087 will want to run its own bus cycles occaisionally.  I don't
	know whether Tandy used these lines or not.

	Mike McNally
	...allegra!parsec!smu!mike