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From: wm@tekchips.UUCP (Wm Leler)
Newsgroups: crl.general,net.arch
Subject: RISC & Smalltalk
Message-ID: <691@tekchips.UUCP>
Date: Wed, 11-Apr-84 18:11:37 EST
Article-I.D.: tekchips.691
Posted: Wed Apr 11 18:11:37 1984
Date-Received: Sat, 28-Apr-84 08:07:26 EST
Organization: Tektronix, Beaverton OR
Lines: 20

In the just-out issue of Computer Architecture News (v12, #1,
March 84) there are two articles about RISC architectures.

The first one runs benchmarks the RISC I.  They were trying to
eliminate differences in performance caused by using different
compilers, *and* they eliminated the register window scheme, and
the RISC still performed as well as a 68000 or a Z8000.

The second one is a report on the RISC II by David Patterson.
Pretty slick.  They have some benchmarks for a large program,
and some estimates for other RISC architectures, including an
ECL RISC implementation that would fit on one board.

This paper "concludes with a short description of our next
project,"  "Smalltalk on a RISC, or SOAR."  They hope that
"SOAR will show that a Reduced Instruction Set Computer can
be a low cost, high performance Smalltalk machine."

				Wm Leler
				tekchips!wm