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Path: utzoo!linus!philabs!hhb!jon
From: jon@hhb.UUCP (John Sissler)
Newsgroups: net.unix-wizards
Subject: pyramid architectural restraints
Message-ID: <120@hhb.UUCP>
Date: Thu, 19-Apr-84 12:00:54 EST
Article-I.D.: hhb.120
Posted: Thu Apr 19 12:00:54 1984
Date-Received: Sat, 21-Apr-84 02:47:26 EST
Organization: HHB-Softron, Mahwah, NJ
Lines: 11

We currently have a pyramid 90x which I am evaluating in my copious spare
time.  It's configured with 4m main, and ~900m disk.  We do not have
data cache installed yet.  So far, a great deal of fun has been had, but
the 90x faults on non-long-aligned 32-bit memory operations.  Any comments,
questions, opinions, etc, would be of interest.  Especially regarding the
above item.  Also, I am interested in exchanging benchmark stats (vs
780, 750).  Lastly, I am curious about up-and-coming architectures (exp.
DEC) with the above constraint.  

			{decvax|ihnp4|allegra}!philabs!hhb!jon