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Path: utzoo!watmath!clyde!burl!mgnetp!ihnp4!inuxc!pur-ee!uiucdcs!uicsg!sharma
From: sharma@uicsg.UUCP
Newsgroups: net.arch
Subject: Re: disappointing supercomputer? - (nf)
Message-ID: <3200005@uicsg.UUCP>
Date: Tue, 15-May-84 22:10:00 EDT
Article-I.D.: uicsg.3200005
Posted: Tue May 15 22:10:00 1984
Date-Received: Fri, 18-May-84 00:30:31 EDT
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Nf-From: uicsg!sharma    May 15 21:10:00 1984

#R:hhb:-15200:uicsg:3200005:000:430
uicsg!sharma    May 15 21:10:00 1984


Cray-XMP Memory Cycle Time:

	The Cray-XMP memory consists of 32 banks - organised as 4 lines with
8 banks each. The two CPUs each have three memory ports and one I/O port.
These four ports are connected directly to the four lines.
	The memory access time is 4 cycles ( 4 times 9.5 nsec ) i.e. each
bank can accpet a request every 4 cycles. Each line, however, accepts
a request every cycle.


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