Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site decwrl.UUCP
Path: utzoo!watmath!clyde!akgua!sdcsvax!dcdwest!ittvax!decvax!decwrl!baskett
From: baskett@decwrl.UUCP
Newsgroups: net.arch
Subject: Re: "another RISC" machine
Message-ID: <332@decwrl.UUCP>
Date: Sat, 19-May-84 17:12:32 EDT
Article-I.D.: decwrl.332
Posted: Sat May 19 17:12:32 1984
Date-Received: Mon, 21-May-84 03:10:06 EDT
Organization: DEC Western Research Lab, Los Altos, CA
Lines: 46

<>
While discussing Pyramid, Mark Weiser claims the Ridge 32 is not
"another RISC" machine because it doesn't have register banking.

The first machine I know of to have register banks that interacted
with procedure calls was the MAC-8, an 8-bit microprocessor done at
Bell Labs sometime in the dark ages of the the 1970's.  Then TI
picked up the idea in the TI 9900 microprocessor but blew the
implementation rather badly.  Dick Sites tried to get people back
on the track with a paper he gave at the first annual Caltech
Conference on VLSI, "How to use 1000 registers" in January
of 1979.  We did some experimental simulation studies on this
scheme at Stanford and I presented those results at a talk at
Berkeley in the fall of '79.  Patterson and company decided
to incorporate this idea into their then just starting
microprocessor design project.  I don't remember when they
started calling it the RISC project.  Pyramid was then influenced
by the subsequent work at Berkeley.

However, "RISC" is an acronym for "Reduced Instruction Set Computer".
The idea of reduced instruction set computers is mostly orthogonal
to the use of register banks that interact with procedure calls.
The RISC idea grew out of the many studies of static and dynamic
instruction frequencies done in the 60's and 70's, mostly on 360's
and 370's, that showed that the lion's share of the computing work
was done by a small subset of the simple instructions.  My favorite
example result was Len Shustek's showing that for speed of execution,
sequences of loads or sequences of stores were better than single
load multiple or store multiple instructions on the 370/168.  The
cross over point was 15 registers and the average number was 4!
Some of these studies were at least partially motivated by the
desire to understand how Seymour Cray could build such fast machines
while the rest of the world just poked along.  And by 1979 word
had already begun to leak out of the IBM Yorktown Heights 801
project that a very simple machine with little or no microcode
might be "the thing to do".

Thus we might say that the Pyramid machine is NOT a RISC machine
because it has moderate amounts of microcode rather than saying
that it is a RISC machine because it has register windows.
Likewise, the Ridge machine would not be a RISC machine because
it also has a moderate amount of microcode.  (Yes, we know that
the marketing departments at Pyramid and Ridge have already
asserted that their machines are RISC machines.)

Forest Baskett - Digital Equipment Corporation - Western Research Lab