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Path: utzoo!watmath!clyde!akgua!mcnc!philabs!hhb!jon
From: jon@hhb.UUCP (John Sissler)
Newsgroups: net.arch
Subject: RISCy assertions...
Message-ID: <159@hhb.UUCP>
Date: Mon, 21-May-84 22:58:44 EDT
Article-I.D.: hhb.159
Posted: Mon May 21 22:58:44 1984
Date-Received: Sat, 26-May-84 09:12:17 EDT
Organization: HHB-Softron, Mahwah, NJ
Lines: 27


	To all involved in the Pyramid RISC discussion:

	I was under the impression (naive perhaps) that one of the
primary goals of the RISC architecture was to provide an instruction set 
whose members all roughly shared execution times.   This allowed the
implementation of a cheap, multi-stage pipeline.  A complex instruction set
carries with it the burden of vastly different execution times, not
exactly an advantage to the architect trying to control a multi-stage pipeline.
Remember, pipelining is the greatest idea since cache, one for the memory sub-
system, one for the processor!

	What does register banking have to do with the basic concept of
homogeneous execution times?

	As a last note, if you want raw I/O or processor speed, you 
probably have to pay ($) for it.  The pyramid is a fantastic, cost
effective machine, don't humble the poor thing with raw processor
benchmarks,  the register banks don't quite hum in a compute bound-
looping C-function!

		john - HHB-Softron ...

" the people who brought you the original 90x non-aligned 32-bit move!"

UUCP address: {decvax,allegra}!philabs!hhb!jon