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From: vifl@hou2f.UUCP (M.MEKETON)
Newsgroups: net.micro,net.lang.apl
Subject: Benchmark:  APL.68000 vs APL*PLUS/PC w/8087
Message-ID: <233@hou2f.UUCP>
Date: Wed, 23-May-84 10:49:44 EDT
Article-I.D.: hou2f.233
Posted: Wed May 23 10:49:44 1984
Date-Received: Sat, 26-May-84 10:19:32 EDT
Organization: AT&T Bell Labs, Holmdel NJ
Lines: 95

I received a brochure from The Computer Company on their APL.68000,
which is an APL interpreter for Motorola 68000 computers.  It runs
on LISA's, WICAT's, FORTUNE 32:16's, IBM CS9000's, and a number of
other 68000 based micro's.  The cost is between $500 and $3000, with
the most likely cost of $2000 (cost varies from machine to machine,
depending on the number of simultaneous users, etc.).  It runs under
UNIX, XENIX, CP/M 68K, and a number of other operating systems.  In
general, it seems to be a very competent APL.

The brochure included a table of benchmarks that compared the APL.68000
running under a 8 MHZ 68000 chip with 0 wait states to (among other
computers) the IBM PC running STSC's APL*PLUS/PC with no 8087 chip.

I felt that an interesting comparision would be to see the performance
of APL*PLUS/PC with an 8087 chip, so here goes:

________________________________________________________________________
All times are in milleseconds, the first three columns are a copy
of the APL.68000 published benchmark, the fourth column are my timings,
with each operation being duplicated 100 times and averaged.

Benchmark		APL.68000	APL*PLUS/PC	APL*PLUS/PC
					w/o 8087	w/ 8087
-------------------------------------------------------------------
Plus Reduction		12.50		158.73		36.8
Z #is +/VI

Logical Reduction	1.24		6.04		9.3
Z #is #or/VL

Maximum Reduction	7.19		27.46		39.0
Z #is #maximum/[1]MI

Exponentiation		909.99		2476.04		299.3
Z #is VI*.5

Absolute Value		55.62		129.07		74.2
Z #is |VR

Indexing		9.37		16.48		33.6
Z #is VR[VI[#count 20]]

Sorting			109.06		156.07		127.4
Z #is VI[#downgrade VI]

Take			2.50		26.91		33.6
Z #is "2 1 #take MR

Membership		121.87		147.75		162.0
Z #is VI #member VI

Transposition		94.68		69.75		74.7
Z #is 2 1 #transpose MC

Outer Product, (char.)	80.00		134.02		145.6
Z #is VC #outer = VC

Outer Product, (int.)	113.43		450.39		446.4
Z #is (#count 50) #outer + #count 50

Inner Product, (real)	113.75		547.07		288.4
Z #is VR #minimum . + VR

Matrix Division		288.12		2166.81		209.9
Z #is MR #solve 10 #take VR

Fibonacci Series	938.00		3515.23		2487.4
Z #is 1 1
L:#goto (100>#shape Z #is Z,+/"2 #take Z)/L

Variables used in the benchmark:
MI #is 10 10 #reshape VI #is (500 #reshape 0 1 0 0 1)/#count 500
VL #is 1 0 1 1 0 0 0 1
MR #is 10 10 #reshape VR #is VI+0.1
MC #is 26 26 #reshape VC #is 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'

(I used the keyword form of APL established by STSC in place of the
 unusual APL symbols)

When the operation clearly used the 8087 chip, such as exponentiation
and matrix division, the 8087 chip contributed to a reduction by a
factor of 10.  Some other real number operations were reduced in half.
I do not understand why some of my times were actually higher that the
w/o 8087 times.

More important, this shows that the IBM PC with the 8087 chip, running
floating point operations, performs comparably to the 68000 chip
which doesn't have hardware floating point support.  The 80186 chips,
if they are coupled with the 8087 chips (can they be?) would be a
forminable contender to the 68000 chip - in terms of speed.

As usual, I do not represent any of the companies mentioned.

Marc S. Meketon
hou2f!vifl