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Path: utzoo!linus!vaxine!wjh12!genrad!decvax!ittvax!dcdwest!sdcsvax!sdcrdcf!hplabs!cygnet!bob
From: bob@cygnet.UUCP
Newsgroups: net.micro
Subject: Re: net.digital - is FAST really needed
Message-ID: <488@cygnet.UUCP>
Date: Sat, 26-May-84 15:43:38 EDT
Article-I.D.: cygnet.488
Posted: Sat May 26 15:43:38 1984
Date-Received: Wed, 30-May-84 00:10:23 EDT
References: <591@decwrl.UUCP>
Organization: Cygnet Systems -- Sunnyvale, CA
Lines: 17

[I hope this works - this is my first posting]
I'm curious about where you guys are getting your numbers for 
metastable settling times.  About 6 years ago I did some playing 
around in the lab trying to induce metastability in LS, ECL 10k, and 
CMOS, but my attempts were rather clumsy and could only give me a 
general feel for the characteristics of the family.  

I had the idea of doing an analysis of the behavior of various logic 
families using SPICE, but figured that to do it properly would require 
getting device characteristics from the chip houses.  I assumed that 
they would not be willing to let the information out.  

Do any of you know of serious work that characterizes the various
families and is in the public domain?

Bob Clark
Cygnet Systems, 610 Palomar Ave., Sunnyvale, CA 94086 (408)773-0770