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From: phil@amd70.UUCP (Phil Ngai)
Newsgroups: net.micro,net.arch
Subject: Re: net.digital: low overhead refresh controller?
Message-ID: <4691@amd70.UUCP>
Date: Thu, 31-May-84 22:01:40 EDT
Article-I.D.: amd70.4691
Posted: Thu May 31 22:01:40 1984
Date-Received: Sat, 2-Jun-84 11:48:15 EDT
References: <1179@sun.uucp>
Organization: AMD, Santa Clara, CA
Lines: 15

This is an attractive idea because the refresh overhead is real and
noticable. It is complicated by multiple banks of memory (the banks
which are not accessed are still eligible for refreshing). The idea
of using a refresh controller per bank sounds expensive in $ and board
space. Because of the large number of pins (18 address in, 9 address out,
plus control, power and ground) you're probably going to need a 40 pin DIP.

I am assuming you mean to put the entire DRAM control in one chip. If you
want to let another chip do your muxing then you'd need fewer pins. Maybe
even let the address pins be I/O and only need 9.

It is an interesting idea. Maybe a good project for someone
in a LSI design class, or a first CMOS gate array.
-- 
Phil Ngai (408) 749-5286 {ucbvax,decwrl,ihnp4,allegra,intelca}!amd70!phil