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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.micro
Subject: Re: net.digital - is FAST really needed
Message-ID: <3925@utzoo.UUCP>
Date: Sat, 2-Jun-84 18:47:25 EDT
Article-I.D.: utzoo.3925
Posted: Sat Jun  2 18:47:25 1984
Date-Received: Sat, 2-Jun-84 18:47:25 EDT
References: <2539@ecsvax.UUCP>, <1135@sun.uucp>
Organization: U of Toronto Zoology
Lines: 18

Thinking of edge rates brings to mind something I've been curious about
for some time.  The spec sheets for practically any digital logic give
a maximum edge time, for obvious reasons.  But one or two spec sheets --
notably for the 64K DRAMs -- also specify a *minimum* edge time.  Does
anybody know why?  (I'm not up on the intricacies of MOS VLSI.)  Is
this just a matter of "our testers won't run any faster than this, and
we won't guarantee behavior we don't test", or is there some problem
with very fast edges?

Specifically, suppose that I'm driving 64Ks with 74F drivers, and I'm
half-asleep and hence have forgotten the series damping resistors.  The
poor DRAM is now getting a direct look at those sizzling-fast 74F edges.
Will it go up in a puff of glittering smoke?  Will it just refuse to work?
Will it hold a secret grudge against me, so that it fails later when I'm
depending on it?  Or what?
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry