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From: bcase@uiucdcs.UUCP
Newsgroups: net.arch
Subject: Re: Z800 -- any information ? - (nf)
Message-ID: <27800019@uiucdcs.UUCP>
Date: Sat, 21-Jul-84 16:59:00 EDT
Article-I.D.: uiucdcs.27800019
Posted: Sat Jul 21 16:59:00 1984
Date-Received: Sun, 22-Jul-84 06:21:00 EDT
References: <797@glasgow.UUCP>
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Nf-ID: #R:glasgow:-79700:uiucdcs:27800019:000:2148
Nf-From: uiucdcs!bcase    Jul 21 15:59:00 1984

#R:glasgow:-79700:uiucdcs:27800019:000:2148
uiucdcs!bcase    Jul 21 15:59:00 1984

I have the new Zilog data book in which the Z800 is described.  The idea
is basically to integrate an enhanced Z80, memory management, and a cache
on one chip.  They seem to have thought of most things, e.g. the cache
can be a cache or just some on-chip RAM with especially fast access.  They
also have pipelined the implementation of the Z80, so that it should be
quite a bit faster than the old chips.  They say that 10 MHz chips will
be available initially, but that chips capable of handing clock rates of
up to 25 MHz will eventually be sold.

You may also be interested in knowing about the Z80000, Zilog's 32-bit
microprocessor.  Compatable with the Z8000 stuff, it also has an on-chip
cache (256 bytes organized as 16 lines of 16 bytes, same for the Z800),
an on-chip TLB for true virtual memory, a pipelined implementation (6
pipe stages!!  Yeech!!!), and a multiplexed, 32-bit data/address bus.
The Z80000 cache can be configured to cache data only, instructions only,
instructions and data, or turned off.  Also, lines can be locked into
the cache.  The TLB has bits which can declare pages to be non-cacheable
so that junk that doesn't belong there will not screw up the coherency.
The TLB page size is selectable (512, 1024, and 2048 bytes, I think...).
The TLB contains 16 entries, LRU replacement.  Instructions for selective
invalidations in the TLB are provided.  Cache is write-through. They seem to
have thought of most things, considering they had to put everything on chip.
Also initial 10 MHz, later 25 MHz.  My only beef is that they are going
to have a hell of a time doing this in NMOS, and if they had just abandoned
the stupid Z8000 architecture and gone with a RISC-style one, they would
have done much better.  Also, is the 256-byte cache really going to do
much good?  I think 16 TLB entries might be enough, but if it isn't,
what is the poor system designer to do?  I think they should have left
most of this junk OFF CHIP to let people make their own decisions, but
that is just my opinion....

Try getting the data book from Zilog.

    bcase
    Brian Case
    ..!ihnp4!uiucdcs!bcase
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