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From: jds@rlgvax.UUCP (Jack Slingwine)
Newsgroups: net.micro.68k
Subject: Re: The 68010 and MMU's
Message-ID: <2083@rlgvax.UUCP>
Date: Mon, 9-Jul-84 10:47:10 EDT
Article-I.D.: rlgvax.2083
Posted: Mon Jul  9 10:47:10 1984
Date-Received: Tue, 10-Jul-84 08:11:35 EDT
References: <3114@brl-tgr.ARPA>
Organization: CCI Office Systems Group, Reston, VA
Lines: 85

The M68451 predates the M68010, should still be available and
is documented in "M68000 Programmer's Reference Manual (third
edition)" (for availability, see below).

I had (briefly) experimented with the M68010 using the M68451
and everything seemed to work fine.  Based on my experience with
the M68451, you should do your own MMU or wait for Motorola's
(rumored) demand paging MMU chip (the M68451 is not a demand
paging MMU, although it could support some form of virtual memory).

As far as differences between the M68000 and M68010: "M68000
(16/32-BIT MICROPROCESSOR -- Programmer's Reference Manual)
(forth edition)" is the book you want to consult, available
directly from:

	Prentice-Hall, Inc
	Englewood Cliffs, N.J.  07632
	(201) 767-9520

For ~$20 a crack.  This manual documents the M68000, M68008 and
M68010 (but NOT the M68451) (bleed tabs and revision bars indicate
the differences between the different microprocessors).  Differences
between the M68000 and M68010 include:

	Addition of VBR, SFC and DFC registers:

	-	The Vector Base Register holds the address of the
		start of the interrupt vectors (i.e. you can move them
		from "0").
	-	The Source Function Code and Destination Function Code
		registers (when used with the MOVES instruction) give
		you a "better" way of moving between address spaces (i.e.
		kernel to user and back).

	Ability to continue instructions and a "better" exception stack
	layout:

	-	Upon a bus or address error, certain words of the processor
		internal state are dumped onto the stack, allowing
		continuation upon subsequent RTE.
	-	The stacks for all exceptions have the same four words on
		the stack top, bus and address error have their additional
		information below this.

	Addition of new instructions:

	MOVEC	allows you to manipulate the VBR, SFC, DFC and USP.

	MOVES	allows you to move between the address spaces specified by
		the SFC and DFC.

	MOVE from CCR
		allows you to directly examine the condition codes (this
		was formerly done by "MOVE from SR" (see below)).

	RTD	Return and Deallocate -- new linkage primitive.

	Modification of instruction:

	MOVE from SR
		has been made privledged.  This prevents user mode programs
		from determining which mode they're running in (allowing you
		to test operating systems in user mode).

	Definition of eight "breakpoint" illegal instructions:

		0x4848-0x484f cause an illegal instruction exception to
		be generated with a "breakpoint" bus cycle prior to
		exception processing (FC0-2 held high, address lines low);
		this could allow you to trigger a logic analyser.

	Addition of "loop mode" to DBcc instruction:

		A DBcc together with certain one word instructions
		triggers a "loop mode" in which no program fetches are
		generated.  This can be used to effect a "block move"
		instruction with a:

			1$:  move.X (aX)+,(aY)+
			     dbf    dZ,1$

		sequence.

			Jack Slingwine
			{seismo,ihnp4,allegra}!rlgvax!jds