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From: gnu@sun.uucp (John Gilmore)
Newsgroups: net.micro.68k, net.micro.16k
Subject: 68020 production samples announced
Message-ID: <1543@sun.uucp>
Date: Thu, 12-Jul-84 09:40:37 EDT
Article-I.D.: sun.1543
Posted: Thu Jul 12 09:40:37 1984
Date-Received: Sat, 14-Jul-84 02:18:35 EDT
References: <579@islenet.UUCP>, <120@dice.UUCP>
Organization: Sun Microsystems, Inc.
Lines: 36

According to Electronics, July 12, page 46 and pg 130:

Motorola is offering 68020 samples that run at 12.5MHz and cost $487.
Initial production of 16.67MHz parts is expected in early 1985, with
volume production in the 2nd quarter.  At 16.67MHz, it runs 68000 code
at 2.5 MIPS continuously, or up to 8 MIPS in bursts, while drawing only
1W.  This is 3.25 times as fast as the 68000 and much faster than a Vax
780.  (They delayed it by 6 months to incorporate more high-speed CMOS,
reducing the power from 2.5W and upgrading the speed from 1.5 MIPS.)

The address and data buses are both 32 bits (it comes in a 114-pin
pin-grid array) and it deals on-the-fly with misaligned storage
references as well as 8-bit, 16-bit, and 32-bit memories and
peripherals.  On each access, the peripheral tells it how much data was
accepted or provided; if there is more, the 68020 will run further
cycles at higher addresses until it's all accepted.  The bus design
is very elegant and easy to interface with.

There is a 68020 User's Manual which, like the 68000 Fourth Edition
manual, is published by Prentice-Hall.  The instruction timings are out
of this world -- the charts are 20 pages, plus 8 pages of text which
explains with colored examples that because of the pipelining you can't
rely on the charts.  It has a 256-byte cache on-chip for instructions,
incurring no prefetch delays for instructions which are in the cache,
and overlapping their execution with bus cycles generated by previous
or following instructions.

The instruction set is a superset of the 68010, including full 32-bit
displacements everywhere, scaled indexing, and memory indirect
addressing modes.  There are 32x32->32 multiply and divide as well as
the traditional 32x32->64 variants.  Rational bit (and bit-field)
addressing instructions are included.  They threw in a few goodies for
ring-style protection systems and separate interrupt and supervisor
stacks, as well as a truly general coprocessor interface, unlike the
warts put out by Intel and National that hook up their float chip
and nothing else.  All in all, not a bad deal for $500.