Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83 SMI; site sun.uucp Path: utzoo!watmath!clyde!burl!ulysses!mhuxl!houxm!houxz!vax135!cornell!uw-beaver!tektronix!hplabs!sdcrdcf!sdcsvax!akgua!mcnc!decvax!decwrl!sun!gnu From: gnu@sun.uucp (John Gilmore) Newsgroups: net.micro.68k,net.micro.16k Subject: Re: Warty Intel co-processor interface Message-ID: <1559@sun.uucp> Date: Wed, 18-Jul-84 22:17:48 EDT Article-I.D.: sun.1559 Posted: Wed Jul 18 22:17:48 1984 Date-Received: Tue, 24-Jul-84 03:41:58 EDT References: <579@islenet.UUCP>, <120@dice.UUCP>, <1543@sun.uucp> <4089@utzoo.UUCP> <337@intelca.UUCP> Organization: Sun Microsystems, Inc. Lines: 37 I do SO love it when people spout off about things they seem to know little about. I do suppose, however, that all of this really matters in how you define "coprocessor." WRT the 8086, ... Ken Shoemaker, Intel, Santa Clara, Ca. {pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!kds Actually I was talking about the 80286/80287. Intel refuses to document the coprocessor interface (that should give you a clue right there), so what follows is from guesses and experience rather than specs. The 286 decodes the floating point instructions and turns them into references to I/O addresses 0xF8, 0xFA, and 0xFC. The 287 is wired into the I/O decoding such that these addresses cause chip selects. Typical instructions cause a read to 0xF8 (status register) to check for busy, followed by writing the opcode to 0xF8. It then writes the PC and EA to 0xFC, in case a fault occurs. The 286 then waits for the 287 to issue PEREQ; this indicates that an operand is wanted. The 286 fetches the operand and writes it to 0xFA, while asserting PEACK. (The 286 -- the CPU, not the float chip -- knows where the operand is, and how many bytes it occupies.) When the 286 has transferred all the operand bytes, it continues with the next instruction. The 286 and 287 microcode implements seven different variants of this protocol, depending which float instruction is involved. This is not a terrible way to attach a float chip. However, it does not let you add arbitrary instructions to the instruction set, which is the whole point of a general coprocessor interface. Nor does it let you have two coprocessors even if the wired-in EA and operand size decoding could be worked around -- so if you build a graphics coprocessor you'll have to give up floating point. The 68020 provides all these capabilities. ---the above views are personal. They may not represent those of Intel.