Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: notesfiles
Path: utzoo!watmath!clyde!burl!ulysses!mhuxl!houxm!vax135!cornell!uw-beaver!tektronix!hplabs!hp-pcd!hpisla!hplvla!gt
From: gt@hplvla.UUCP (gt)
Newsgroups: net.lsi
Subject: Re: Need Project for VLSI Class
Message-ID: <21300001@hplvla.UUCP>
Date: Sun, 12-Aug-84 16:55:00 EDT
Article-I.D.: hplvla.21300001
Posted: Sun Aug 12 16:55:00 1984
Date-Received: Mon, 3-Sep-84 09:39:42 EDT
References: <1030@tekchips.UUCP>
Organization: Hewlett-Packard - Loveland, CO
Lines: 26
Nf-ID: #R:tekchips:-103000:hplvla:21300001:000:726
Nf-From: hplvla!gt    Aug 29 12:55:00 1984

<<<           >>>

First, I wouldn't worry about it being "fun to have after class was
over" since class chips have about a .0001 chance of working anyway.

Suggestions:

	. An associative RAM chip would be fun.  There are lots of
	paper designs floating around but few ever make it to 
	Silicon.  The challenge is in trying to reduce the number
	of transistors in your cell (I think I've seen nine?) and
	making it wide and fast.  Besides, the layout is easy.

	. A Silicon sorter is a good project; the design takes 
	a bit of time though.

	. A three input NAND gate is a good backup project to 
	keep in reserve.


	good luck


                   George Tatge
		   HP Loveland Instrument Div.
		   ihnp4!hpfcla!hplvla!gt