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From: padpowell@wateng.UUCP (PAD Powell)
Newsgroups: net.lsi
Subject: Re: Self timed vs synchronous, lets discuss
Message-ID: <1393@wateng.UUCP>
Date: Wed, 5-Sep-84 08:22:26 EDT
Article-I.D.: wateng.1393
Posted: Wed Sep  5 08:22:26 1984
Date-Received: Thu, 6-Sep-84 04:17:03 EDT
References: <265@rochester.UUCP>, <18@sdcsvax.UUCP>, <3019@utah-cs.UUCP>
Organization: U of Waterloo, Ontario
Lines: 43

O.K., O.K.- I said that I looked at testing self timed circuits, and
shuddered.  Somebody said that selftimed are "no harder to debug" ...
using "a couple of lights and a logic probe".  I have the most hilarious
picture of me sitting at a binocular microscope, probing a wafer...

I should have said that "designing a self timed chip which is easily testable"
seems to be a major problem.  I have had several thoughts that would seem
to make the job feasible, but perhaps not simple.

First, one of the techniques in designing testable circuits is to partition
the design into blocks of combinatorial logic, separated by latches/shift
registers.  Circuitry is provided to externally load the shift registers
with a value is used to "probe" the combinatorial logic.  The output of the
combinatorial logic can be latched, and resused to generate new values,
or read out, and checked for a correct value.  There are many variations on this
them, published in proceedings, conferences, etc.  Keywords are BILBO,
LSSD (Level Sensitive Scan Design), Self Testing, etc.

If a self timed system is designed with the data tranfer paths between
blocks to have latches/shift registers placed in critical places, then
it is possible to use the same method to test the logic blocks.
Now you have to figure some way of testing the self time circuitry.

I was playing around with some self timed controller circuits, and noticed
that they all seemed to incorportate some memory elements;  I wondered
if they couldn't be used as a shift-register latch.  No, not quite, but
you could use them as "pass-through/shifters"; now what you could do would
be to fake up a set of "syndrome tests", load these values into the
pass-through/shifters externally, then enable the logic.  By enabling
a critical set of the latches at a time (much handwaving at this point)
and then looking at the values/using them to generate more,
it should be possible to generate tests.

What is the big problem?  Designing test sequences.  I have heard from
people that designing test sequences for asychronous logic is the most
difficult part of test engineering.   Comments like "The stupid program
ran for 60 HOURS on a Mach IV, with a Gigabyte/Megaflop unit, and only
gave me 90% coverage" seems to be common...  The partitioning of the
logic seems to simplify the problems, and and make better test generation
feasible, but not EASIER.

Patrick ("Test? what is this test B.S.?  Real engineers use scopes and
	logic probes!") Powell