Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site utah-cs.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxl!houxm!vax135!cornell!uw-beaver!tektronix!hplabs!utah-cs!stevens From: stevens@utah-cs.UUCP (Ken Stevens) Newsgroups: net.lsi Subject: Re: Self timed vs synchronous, lets discuss Message-ID: <3019@utah-cs.UUCP> Date: Sun, 9-Sep-84 01:24:13 EDT Article-I.D.: utah-cs.3019 Posted: Sun Sep 9 01:24:13 1984 Date-Received: Thu, 6-Sep-84 04:20:51 EDT References: <265@rochester.UUCP>, <18@sdcsvax.UUCP> Organization: Univ of Utah CS Dept Lines: 96 In general, curcuit designers are quite ignorant of the attributes of asynchronous circuits, as witnessed by previous comments. It is totally wrong that self-timed circuits are harder to debug (they are actually much easier to debug). Unfortunately, most of these myths are propagated by people who have little knowledge or experience in the design of self-timed circuits. Comparing asynchronous and synchronous circuits is analogous to comparing FORTRAN with functional or object oriented languages. There are certain advantages to the functional style, although you can do anything in FORTRAN that you could in LISP, just as you can do anything with a synchronous circuit that you could with an asynchronous one (but I can't figure out why anyone would want to!). Some of the advantages: * Easier to make abstractions * The constraints for elements are local, rather than global * Self-timed circuits are highly modular * Elements are directly replacable by improved versions * Easier to debug * Copes with problems of improved technology THE MAIN DIFFERENCE: Function and sequencing are necessary elements for any design to work. However, synchronous circuits also require the additional constraint that requires events to occur during an absolute time window. In some ways this is good, in others it is bad. It allows designers to be somewhat sloppy and allow certain types of races and glitches, so long as the circuit is stable by the end of the clock period. That is a big win. Self- timed circuits will not function correctly with glitches, races or hazards. EASIER TO ABSTRACT: The LSI designer benefits greatly from the ability to abstract through block diagrams, logic diagrams, stick diagrams, etc. In async circuits, this abstraction applies directly to the actual timing of the circuit. Smaller self-timed elements are used as functional black boxes to build larger systems, and the only constraints necessary are those directly applicable to the current level of abstraction. A functional description alone is not sufficient information to build and interface synchronous circuits. LOCALITY OF CONSTRAINTS: In FORTRAN, globals and commons are generally used, whereas in an applicative language their usage is rare. Most constraints in computations in self-timed systems are also local. Each element has it's own speed, critical path, storage nodes, etc. There is no concept of global critical path analysis or timing verification. Data is passed as a parameter to an element along with a request to process the data. MODULARITY: Asynchronous systems are extremely modular. Larger systems are simply built out of smaller ones. This aids in replacability and debugging. Each module can be viewed as a black box-- request a function with data, and some unknown (but hopefully short) time later the answer will be returned. REPLACEABILITY: Because of the modularity, all elements in self-timed systems are replaceable. For example, I had a design where a slow ripple-carry counter was used. I replaced the slow counter with a fast full lookahed counter, and there was no need to similate or verify the change. The only difference came in a possible area missmatch and quicker circuit. DEBUGGING: At the functional level, sync and async circuits are equally hard to debug. Asynchronous circuits generally require more care in the design since timing must be generated internally and there may not be races or hazards. However, once the functional element is designed, you are way ahead because self-timed SYSTEMS are much easier to debug than synchronous ones. There is no global clock driving the error ahead. If a self-timed system fails, you can generally go to lunch, get your tool box, and nothing will have changed. There is also no real need for expensive equipment such as logic analyzers, etc. The system can be debugged with a switch and light panel and logic probe. The handshaking signals can be intercepted in between each module, and you have all the time you desire to examine the data. The most common problems are that the function you specified was not really what is required, or the signals were connected wrong. An interesting observation: In the vast majority of the cases, a failure in self-timed systems will cause the machine to hang. From there it is usually quite clear where the fault originated. FUTURE TECHNOLOGY: Just as functional languages adapt better to AI and the newer technology, self timed systems adapt much better to decreased lambda and tau. Global synchrony on a chip will likely be impossible in the future. Speed independent designs are scaleable and will still function at lambda = 0.25u, just as they did at lambda = 2u. SPEED: If the granularity of self-timed systems is small, sync systems will be faster because the overhead for the handshaking operation will be a substantial fraction of the time required to carry out the desired function. Again, as in debugging, self-timed systems, if designed correctly, can be much faster than synchronous systems. This is due to the fact that there is no need for components to run at worst-case speeds, there is no need for concurrent operations to run at nearly the same speed, etc. SUMMARY: Hopefully this dispells some of the myths which surrounds self-timed circuits. Given my choice I would much rather design self-timed circuits! I suggest that you read Mead-Conway chapter 7 by Chuck Seitz for a good treatment of timing methodologies. cheers harpo!utah-cs!stevens stevens@utah-20