Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site loral.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxl!houxm!vax135!cornell!uw-beaver!tektronix!hplabs!sdcrdcf!sdcsvax!sdccs6!loral!ian From: ian@loral.UUCP (Ian Kaplan) Newsgroups: net.micro.68k,net.arch,net.lang Subject: Re: Inconsistent bit addressing in the 68020: big- AND little-endian Message-ID: <444@loral.UUCP> Date: Fri, 24-Aug-84 13:55:08 EDT Article-I.D.: loral.444 Posted: Fri Aug 24 13:55:08 1984 Date-Received: Sat, 1-Sep-84 09:59:32 EDT References: <491@turtlevax.UUCP> Organization: Loral Instruments, San Diego Lines: 17 In Ken Turkowski's article on the big and little endian addressing used on the 68020 he commented that Motorola's approach "proved" that a machine with consistant bit addressing (e.g., all little or big endian) was impossible. I assume that he was joking. If not perhaps a follow up article could be submitted clairifing this. It is becoming widely recognized that consistant (or orthogonal) instruction sets are a desirable architectural feature. (The NS32016 instruction set is one example of an orthogonal instruction set.) If consistant instruction sets are desirable, then it seems obvious that consistant bit addressing is also desirable. Ian Kaplan Loral Data Flow Group Loral Instrumentation ucbvax!sdccsu3!loral!ian