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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.micro,net.misc
Subject: PAL and tri-state gate outputs
Message-ID: <399@intelca.UUCP>
Date: Mon, 10-Sep-84 17:56:45 EDT
Article-I.D.: intelca.399
Posted: Mon Sep 10 17:56:45 1984
Date-Received: Sun, 16-Sep-84 10:32:23 EDT
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 21

(does net.digital exist?  we don't have it locally...)

Anyway, does anyone know if tri-state outputs on PALs are guaranteed
not to glitch entering/leaving tri-state?  Here is what I need: the
function is driven high, then tri-stated.  All during the time it
is tri-stated, the function remains high.  It then goes out of tri-state
before the function is driven low.  Finally, after it is out of
tri-state the function is driven low.  At each of the transitions
into and out of tri-state, it is very important that the output not
glitch low!  Of course, the output will be provided with some kind
of tie-up resistor.  What I need is some kind of confirmation that
PAL outputs (or any tri-state gate outputs, for that matter) don't
do funny things going into and out of tri-state.
-- 
I've got one, two, three, four, five senses working overtime, 
	trying to take this all in!

Ken Shoemaker, Intel, Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!kds
	
---the above views are personal.  They may not represent those of Intel.