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From: klr@lems.UUCP (Ken Robbins)
Newsgroups: net.arch
Subject: Re: byte alignment
Message-ID: <133@lems.UUCP>
Date: Wed, 17-Oct-84 12:37:11 EDT
Article-I.D.: lems.133
Posted: Wed Oct 17 12:37:11 1984
Date-Received: Tue, 23-Oct-84 01:17:23 EDT
References: <426@ima.UUCP> <opus.883>
Reply-To: klr@lems.UUCP (Ken Robbins)
Organization: lems
Lines: 17
Summary: 


I am new to the net and I seem to have got the tail end of these discussions
on byte alignment.  For those of you interested in arbitrary byte alignment
as well as variable length data (as opposed to just byte, word, long
etc.) you should probably take a look at INTEL's iAPX series of microprocessors.

It's been over a year since I have looked at the architecture of this chip,
and I don't seem to have the data sheets handy, so take this with a grain of
salt.  The iAPX grabs its data in nibbles, and is designed to gobble up strings
(of arbitrary length) of nibles to form data words that are multiples of
nibbles.  Therefore, this chip (actually chip set) is is not constrained by
byte alignment or data width.
  There are quite a bit of progressive architecture features of the iAPX series,
I will try to get a hold of the data sheets and summarize some of the salient
features. If anyone else on the net knows about, or especially has used this
series, it would be great if they could post their experiences and knowledge.
      Ken