Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site drivax.UUCP Path: utzoo!linus!decvax!decwrl!amd!fortune!hpda!hplabs!amdahl!drivax!alan From: alan@drivax.UUCP (Alan Fargusson) Newsgroups: net.arch Subject: Re: byte alignment Message-ID: <47@drivax.UUCP> Date: Mon, 29-Oct-84 12:58:59 EST Article-I.D.: drivax.47 Posted: Mon Oct 29 12:58:59 1984 Date-Received: Fri, 2-Nov-84 04:12:10 EST References: <426@ima.UUCP> <133@lems.UUCP> Organization: Digital Research, Monterey Lines: 25 You must be thinking of the 432. The iAPX286 is a 16 bit machine, and if you access a word that is not aligned it does two byte accesses. This causes a performance penelty that seems rather high by Intels own benchmarks. I think you will find that the other iAPX*86 products are much the same in this respect. While I am on the subject, it seems to me that the real problem is in the implementation. If you design hardware to handle byte alignment it should be just as fast to access missaligned words as aligned words. This would be more expensive of course, but if you need to do it in software it is much slower. An aside: I wrote a device driver for the Intel iSBC 215 (for UN*X sVr2). This device uses ram for control blocks. Two of the fields in the error status block are missaligned, and one in the format block is missaligned. Our compiler alignes words, so I had to declare these fields as chars, then make an int pointer to the first char to access the words. It is kind of a pain, and the code is less clear than I would like. If hardware designers don't want to make efficiant access to missalligned words then they shouldn't missallign words in hardware! (is this a flame?). -- --------------------- Alan Fargusson. { ihnp4, sftig, amdahl, ucscc, ucbvax!unisoft }!drivax!alan