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From: bcase@uiucdcs.UUCP
Newsgroups: net.arch
Subject: Re: 68020 Performance Revisited after re
Message-ID: <27800026@uiucdcs.UUCP>
Date: Thu, 1-Nov-84 13:25:00 EST
Article-I.D.: uiucdcs.27800026
Posted: Thu Nov  1 13:25:00 1984
Date-Received: Sat, 3-Nov-84 03:24:00 EST
References: <4021@decwrl.UUCP>
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Nf-ID: #R:decwrl:-402100:uiucdcs:27800026:000:1205
Nf-From: uiucdcs!bcase    Nov  1 12:25:00 1984

["...she's a line eater..." -- Hall and Oats]

Let me add my two cents to the discussion by agreeing that any sane
68020 implementation will have a data cache.  The Signetics MAC makes
the inclusion of one rather painless, I think.  And the software time
spent invalidating the cache it absolutely of no conern here:  one
cycle (instruction?).  Even a more expensive cache built out of TI's
2150 tag buffer chips would still only require one cycle to invalidate
(assuming, as has been stated, that the cache keys on virtual addresses).

And regarding Falcone's comments:  It seems to me that you are saying
that one VAX MIP is roughly equivalent to 3-4 68000 MIPS (my conclusion
is based on your final table which shows, at 200 ns memory, a 68020
performance of roughly .5 VAX MIPS, while the IEEE paper claims roughly
2.0 68020 MIPS).  This, and correct me please if I have gone astray
here, conclusion seems a little bogus.  The reason:  the average VAX
instruction that gets executed in the average program is not, in my
opinion, 3-4 times more powerful than the average 68020 instruction
for the same program, and the VAX is certainly not operating at 3-4
times the raw speed of the 68020.

    bcase