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From: kissell@flairvax.UUCP (Kevin Kissell)
Newsgroups: net.arch
Subject: Re: 68020 Performance Revisited after reading IEEE Micro
Message-ID: <808@flairvax.UUCP>
Date: Fri, 2-Nov-84 15:47:53 EST
Article-I.D.: flairvax.808
Posted: Fri Nov  2 15:47:53 1984
Date-Received: Sat, 3-Nov-84 21:46:54 EST
References: <4021@decwrl.UUCP>, <1925@uw-june>
Organization: Fairchild AI Lab, Palo Alto, CA
Lines: 15

> Falcone is setting up something of a "straw man" here.  A conscientious
> 68020 design MUST use a data cache, and the data cache keys must be
> VIRTUAL addresses.  

Whether the cache should be virtual or real-address based would seem to 
me to depend on a tradeoff between burning an MMU cycle for every access
(real-address cache) and purging the cache every time the virtual map
changes (virtual-address cache).

Kevin D. Kissell
Fairchild Research Center
Advanced Processor Development
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