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From: haapanen@watdcsu.UUCP (Tom Haapanen [DCS])
Newsgroups: net.arch
Subject: RISC processors
Message-ID: <641@watdcsu.UUCP>
Date: Sun, 11-Nov-84 14:54:53 EST
Article-I.D.: watdcsu.641
Posted: Sun Nov 11 14:54:53 1984
Date-Received: Mon, 12-Nov-84 19:20:30 EST
Organization: U of Waterloo, Ontario
Lines: 41

< Nami nami nami nami ... >

The latest BYTE (should I be ashamed that I still subscribe?  :-) has
an article by John Markoff on RISC (Reduced Instruction Set Computer)
chips.  In particular, the article concentrated on the Berkeley RISC I
and RISC II designs.

Even though the instruction set looks horribly insufficient, I suppose
it could be lived with, especially with the 138 registers RISC I has.
According to the limited benchmarks in the article, the 1.5 MHz RISC I
was able to beat up on a 8 MHz MC68000, and the 5 MHz RISC II runs
'integer C programs' faster than a 10 MHz NS32016 and a 12 MHz MC68000.
The article does not mention how many registers the RISC II has, but
it does say that a 12 MHz RISC II has been fabricated, though.

What I'm wondering about, though, is whether it is feasible to build a
RISC chip in the VAX 11/780 class, i.e. on par with the MC68020 (note:
this is only to imply the the 68020 is in the same *class* as a 780,
not necessarily equal performance).  Apparently the RISC II contains
44,500 transistors, as opposed to the 68020's 200,000, so at least
there is a lot of room to cram more stuff in.  However, will this
improve performance significantly?

The article also vaguely refers to the Pyramid 90x having register
windows.  Does this mean the Pyramid is a RISC design, or does it just
have large register banks?  Are there any other RISC designs and/or
chips commercially available, or will there be in the near future?

Comments would be appreciated, especially from people involved in the
Berkeley RISC or SOAR projects, or the Stanford MIPS project.


Tom Haapanen		University of Waterloo		(519) 744-2468

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