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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: RISC processors
Message-ID: <4624@utzoo.UUCP>
Date: Mon, 12-Nov-84 19:55:53 EST
Article-I.D.: utzoo.4624
Posted: Mon Nov 12 19:55:53 1984
Date-Received: Mon, 12-Nov-84 19:55:53 EST
References: <641@watdcsu.UUCP>
Organization: U of Toronto Zoology
Lines: 55

> Even though the instruction set looks horribly insufficient, I suppose
> it could be lived with...

The whole point of a RISC machine is that you don't live with it; the
compiler does that for you.  So long as it runs his programs quickly,
the nature of the instruction set is not really the customer's concern.
The simplicity makes life lots easier for the compiler and the chip
designer.

> The article does not mention how many registers the RISC II has ...

I think RISC II has roughly twice the register count of RISC I.  Note
that your programs don't get access to all of them simultaneously, so
this is an implementation/performance issue mostly.

> What I'm wondering about, though, is whether it is feasible to build a
> RISC chip in the VAX 11/780 class...

Remember that the current RISC chips are using mediocre MOS processing
and easy-and-simple design rules.  Last I heard, running at the original
target clock speed (which probably hasn't been reached yet), the RISC
design was tentatively benchmarked (by simulation) as substantially faster
than a 780.  This was with, I think, 400-ns memory access times, and an
effective instruction cache was assumed.

> ...  Apparently the RISC II contains
> 44,500 transistors, as opposed to the 68020's 200,000, so at least
> there is a lot of room to cram more stuff in.  However, will this
> improve performance significantly?

If the RISC people got 200k transistors to play with, probably tops on
the agenda would be an instruction cache.  Since the RISC designs execute
a lot of instructions relative to a conventional design, they benefit a
lot from faster instruction fetches.

> The article also vaguely refers to the Pyramid 90x having register
> windows.  Does this mean the Pyramid is a RISC design, or does it just
> have large register banks?

The Pyramid is *claimed* to be more-or-less a RISC design, although from
the sounds of the glossies, they've succumbed to the temptation/need (hard
to tell which) to add tailfins and "features".  Note that it's not a VLSI
RISC, it's a RISC design implemented in ordinary logic.

> Are there any other RISC designs and/or
> chips commercially available, or will there be in the near future?

Don't think there are any other commercial RISC designs just yet, although
there may be half a dozen startup companies about to prove me wrong.  As
far as I know, there are *no* commercial RISC chips at the moment.  The
idea has generated enough enthusiasm that all kinds of people are likely
to jump on the bandwagon in the near future.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry