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Path: utzoo!henry
From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: RISC vs VAX
Message-ID: <4657@utzoo.UUCP>
Date: Mon, 19-Nov-84 17:51:05 EST
Article-I.D.: utzoo.4657
Posted: Mon Nov 19 17:51:05 1984
Date-Received: Mon, 19-Nov-84 17:51:05 EST
References: <1815@inmet.UUCP>
Organization: U of Toronto Zoology
Lines: 22

> ...  RISC architecture is not suited for floating
> point operations, or matrix multiplications, since the arithmetic steps
> produce a very tight bottleneck.  ...

Why?  It is true that the *existing* RISC machines have no floating-point
support, but then neither does the 68000.  This does not imply that one
cannot build an effective floating-point-crunching system around either.

> ...[also, a RISC can't be a VAX] due to the problem of
> i/o on a RISC.  Attaching an ACIA (or similar character-oriented i/o device)
> to the RISC could be a big difficulty -- the cycle times of the two devices
> are different by one or two orders of magnitude.  ...

Uh, Hal, the cycle times of a 780 and an ACIA are also a little bit
different...  So you solve the problem the same way as on the VAX:  if
you want to pump lots of data through the i/o system, the i/o system has
to do some of the work for you.  Actually, this is roughly what your
suggested solution amounts to, except that a VAX cpu is an inordinately
expensive -- and not all that speedy -- i/o processor.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry