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From: kissell@flairvax.UUCP (Kevin Kissell)
Newsgroups: net.arch
Subject: Re: cache designs
Message-ID: <823@flairvax.UUCP>
Date: Sat, 17-Nov-84 04:43:20 EST
Article-I.D.: flairvax.823
Posted: Sat Nov 17 04:43:20 1984
Date-Received: Thu, 22-Nov-84 08:16:54 EST
References: <2571@dartvax.UUCP>
Organization: Fairchild AI Lab, Palo Alto, CA
Lines: 10

Well, the 68020 has cache-control instructions of a sort -  you can freeze 
the on-chip cache.  That's probably worthwhile, because that cache is a little 
small.  I believe that it is preferable to have a cache big enough to get a
90+% hit ratio without intervention than to use dedicated cacheing instructions.

Kevin D. Kissell
Fairchild Advanced Processor Development
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