Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: Notesfiles $Revision: 1.6.2.17 $; site uiucdcs.UUCP Path: utzoo!watmath!clyde!cbosgd!ihnp4!inuxc!pur-ee!uiucdcs!bcase From: bcase@uiucdcs.UUCP Newsgroups: net.arch Subject: Re: cache designs Message-ID: <27800035@uiucdcs.UUCP> Date: Wed, 21-Nov-84 17:19:00 EST Article-I.D.: uiucdcs.27800035 Posted: Wed Nov 21 17:19:00 1984 Date-Received: Sun, 25-Nov-84 03:29:48 EST References: <2571@dartvax.UUCP> Lines: 29 Nf-ID: #R:dartvax:-257100:uiucdcs:27800035:000:1717 Nf-From: uiucdcs!bcase Nov 21 16:19:00 1984 [bug lunch] Your software controlled cache is a very good idea. It is so good that it is being implemented by smart compilers everywhere. If you imagine that the register file of a machine is a cache that must be managed by software, and that at any time, the things in the register file also have home memory locations associated with them, then the code generator (compiler or human being, but the most interesting case is the compiler) or optimizer (as you wish) does the cache managment by emitting the proper load and store instructions. Thus, with a really smart and globally optimizing compiler, a large register file starts to perform like (better than?) a good (great?) data cache. This is one interpretation of your idea, another is honest-to-goodness cache hardware controlled by software. The IBM 801 had some such instructions, but I am not qualified to comment. My point is that your idea is a good one, but it is not really new (sigh, there are no new ideas, only old ones. Many times I thought I had thought of something new, only to read about it in some paper somewhere.). One good place to start reading about this idea is in the paper by Sites "How to use 1000 registers." Although his ideas sound a little like the RISC register file, the essence is there. Then, if you are in to compilers, read about register allocation by coloring and spilling (a paper by some guys at IBM, I can get the reference for you if you are interested) and about register allocation by priority based coloring (by some Stanford guys, Chow and Hennessey). I don't know if anyone has done any work with software controlled instruction caches, but it should be looked into (although it sounds a little scary!).