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From: kissell@flairvax.UUCP (Kevin Kissell)
Newsgroups: net.arch
Subject: Re: cache designs
Message-ID: <830@flairvax.UUCP>
Date: Mon, 26-Nov-84 20:44:58 EST
Article-I.D.: flairvax.830
Posted: Mon Nov 26 20:44:58 1984
Date-Received: Wed, 28-Nov-84 03:14:16 EST
References: <2571@dartvax.UUCP>, <27800035@uiucdcs.UUCP>
Organization: Fairchild AI Lab, Palo Alto, CA
Lines: 11

Cache control by a programmer or compiler differs from register file management
in that cacheing affects both data and program memory accesses, while register 
management has a direct effect only on data memory accesses. Unless, of course,
the registers are addressable as memory by the instruction unit, but not many
contemporary designs have this property.  (As I recall DEC 10's and 20's did).

Kevin D. Kissell
Fairchild Advanced Processor Development
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